Rapid thermal anneal (RTA) is used in semiconductor device fabrication to heat a wafer to alter the wafer's properties, such as to activate dopants, repair damage from ion implantation, transport dopants in or out of the wafer or to other locations within the wafer, etc.
Rapid thermal anneal of a silicon wafer is often effected through direct exposure of the wafer to electromagnetic radiation. Annealing is usually performed after patterning of multiple stacks of dielectric layers on the silicon wafer. When electromagnetic radiation is incident on these stacks, constructive and destructive interference occur due to reflections at each interface in the path of the incident radiation. As a result of the constructive and destructive interference specific to each interface in each stack, the fraction of the incident electromagnetic radiation transmitted (and absorbed) into the silicon wafer is different in the vicinity of different stack-wafer interfaces. Thus the wafer regions are not heated uniformly in these circumstances. The thermal equilibrium length (L) over which thermal equilibrium is achieved can be approximated by L˜(t*k/cv)1/2, where k and cv are the thermal conductivity and specific heat of silicon, respectively, and t is the time scale over which the incident radiation is held at a constant power density. State-of-the-art thermal processing employs electromagnetic radiation on time scales below 0.1 s and as a result thermal equilibrium is not achieved over length scales that are smaller than a typical Very Large-Scale Integration (VLSI) die size.
Thus there is a need to improve the spatial uniformity of thermal annealing of silicon wafers.